In recent times, manufacturing of semiconductor memory devices continuously advance toward high integration and high speed through improvements of technologies, and such devices are used in a variety of products, from large home appliances to small mobile products. A semiconductor memory device typically consists of a plurality of cells which store data therein.
In general, a synchronous memory is provided with a pipe latch circuit for continuous output of the data. The pipe latch circuit functions to store data transferred from a cell region and sequentially output the data to an output driver in synchronization with a clock signal. In this pipe latch circuit, a number of registers varies as a number of data which the pipe latch circuit receives and latches and the number of registers which form the pipe latch circuit is determined in accordance with a CAS latency of the memory device and the like. Also, on the basis of a control method, the pipe latch circuit is divided into a serial pipe latch circuit in which the registers are serially connected and a parallel pipe latch circuit in which the registers are parallelly connected.
FIG. 1 is a block diagram illustrating a configuration of a conventional pipe latch circuit.
The pipe latch circuit as illustrated in FIG. 1 includes a pipe latch control unit 500 and a pipe latch 600.
The pipe latch control unit 500 receives a read-write flag signal RWF, generates first through fourth input control signals PIN<1:4> for latching data inputted to the pipe latch 600 through the global line GIO, and generates first through fourth output control signals POUT<1:4> for controlling an output of data LD latched in the pipe latch 600. Here, the read-write flag signal RWF is a level signal, which is shifted to a high level upon a read operation and shifted to a low level upon a write operation.
The pipe latch 600 sequentially latches the data inputted thereto through the global line GIO in response to the first through fourth input control signals PIN<1:4>, and outputs the latched data LD in response to the first through fourth output control signals POUT<1:4>. If the pipe latch includes four registers, the first register latches the data in response to the first input control signal PIN<1> inputted first, and outputs the latched data LD in response to the first output control signal POUT<1> inputted next. Likewise, the second through fourth registers latch the data in response to the second through fourth input control signals PIN<2:4>, respectively, and then output the latched data LD in response to the second through fourth output control signals POUT<2:4>, respectively.
Meanwhile, the pipe latch control unit 500 is initialized in a period where the read-write flag signal RWF is shifted from a high level to a low level. That is to say, the first through fourth input control signals PIN<1:4> and the first through fourth output control signals POUT<1:4> are all disabled upon transition from the read operation to the write operation, and the enablement is sequentially performed again from the first input control signal PIN<1> and the first output control signal POUT<1> upon next read operation.
However, when the read operation is continuously performed, the pipe latch control unit 500 is not initialized since the read-write flag signal RWF is continuously maintained at a high level and the first through fourth input control signals PIN<1:4> and the first through fourth output control signals POUT<1:4> are maintained at the level upon the previous read operation. For example, if a previous read operation is terminated in a state that the enablement is performed up to the first input control signal PIN<1> and the first output control signal POUT<1>, the enablement begins sequentially from the second input control signal PIN<2> and the second output control signal POUT<2> upon the next read operation. At this time, if the first through fourth input control signals PIN<1:4> and the first through fourth output control signals POUT<1:4> are not matched with each other, the pipe latch can malfunction and cause a read operation failure. For example, there may occur a problem that, if a next read operation begins in a state that the third input control signal PIN<3> is enabled in the previous read operation, the third output control signal POUT<3> is enabled and invaluable data which has been latched in the previous read operation is outputted.